Double data rate synchronous dynamic random-access memory (DDR SDRAM) is a class of memory which has evolved generation over generation every 3-5 years. For the generations of DDR1, DDR2, and DDR3, the input/output (I/O) interface specification is based on Stub Series Terminated Logic (SSTL) I/O electrical standards. For DDR4, the I/O specification is based on Pseudo Open Drain (POD). Other than speed improvement and voltage reduction, a main difference between the two specifications is the termination voltage. For SSTL I/O, the terminated voltage is at the half rail between power and ground, or VDD_IO/2; for POD I/O, the terminated voltage is at the power rail, or VDD_IO. Due to the change of terminated voltage, the specification of strobe signals (referred to as DQS strobe) has also changed.